Published Reports and Visuals

Current FPGA implementation status

• Build 25 is the current production baseline for the XC7A200T target. All timing constraints met. Includes MTI canceller + DC notch filter integration on top of CA-CFAR.
• Build 25 reports are available on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build25/.
• Build 24 (v0.1.5-cfar) retained as pre-MTI reference at reports_build24/.
• Build 21 (v0.1.4-build21) retained as pre-CFAR reference at reports_build21/.

Build 25 — 15-Point Engineering Report

Status: PASS — Production-safe bitstream generated

Date: 2026-03-20  |  Commit: ed629e7  |  Device: XC7A200T-2FBG484I  |  Vivado 2025.2

1. Timing Summary

TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints. Overall WNS +0.132 ns (ft601_clk_in domain, USB FSM path). Overall WHS +0.058 ns.

2. Utilization (Post-Route)

MTI canceller added +694 LUTs (distributed RAM for chirp delay line + subtraction logic + DC notch comparators) and +2,104 FFs (I/Q pipeline registers, saturation logic, notch width comparators). Zero BRAM and DSP impact — MTI uses distributed RAM and fabric arithmetic only.

3. DSP48E1 Breakdown by Module

4. BRAM Breakdown by Module

5. Power Estimate

Power is essentially unchanged (-1 mW). MTI logic is lightweight fabric arithmetic; DC notch is combinational zeroing with negligible dynamic power.

6. Critical Path Analysis

The tightest path (WNS = +0.132 ns) is in the ft601_clk_in (100 MHz) domain: ft601_rxf input pad → 8 logic levels (IBUF + LUT1 + LUT3 + 4×LUT6 + LUT5) → usb_inst/FSM_sequential_current_state_reg[2]/D. This is the USB read FSM path and is unrelated to MTI or CFAR.

The clk_100m domain (where MTI, CFAR, and Doppler operate) has +0.634 ns slack — improved from Build 24's +0.287 ns. The MTI canceller adds no new critical paths.

7. Post-Synthesis vs Post-Route Comparison

Post-route phys_opt resolved all 29 hold violations and improved setup slack by 9 ps. LUT/FF count reduced slightly by optimization passes.

8. DRC (Design Rule Checks)

184 checks performed. 0 errors, 0 critical warnings. Same advisory/warning profile as Build 24 (DPIP-1, DPOP-1/2, REQP-1839/1840, RPBF-3 etc.). No new DRC issues from MTI integration.

9. Methodology Report

Same methodology advisory profile as Build 24. No new methodology warnings from MTI or DC notch logic.

10. Congestion

No congestion windows found above level 5. The design remains well-placed at 6.87% LUT utilization.

11. Route Status

• Total logical nets: 34,325
• Routable nets: 24,510 — 24,510 fully routed (100%)
• Nets with routing errors: 0

12. Hierarchical Utilization — MTI Module

MTI canceller: 544 LUTs (0.40% device), 2,082 FFs (0.77% device), 0 BRAM, 0 DSP. The high FF count is from the chirp delay line (64 range bins × 16-bit I + 16-bit Q = 2,048 FFs for storage) implemented as distributed register file rather than BRAM.

13. Build-Over-Build Comparison

14. MTI + DC Notch Integration Resource Cost

Total MTI + DC notch cost: 0.52% of device LUTs, 0.78% of FFs. Very lightweight addition. Backward-compatible: host_mti_enable defaults to 0 (pass-through), host_dc_notch_width defaults to 0 (off).

15. Verification Summary

5,310 individual data checks across all RTL test suites. Zero failures. MTI standalone test covers: pass-through, first-chirp mute, subtraction correctness, stationary target cancellation, moving target preservation, saturation (positive/negative), enable toggle, reset behavior, bin tracking, back-to-back chirps, and negative value handling.

Build 25 Artifacts

• Bitstream: ~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build25.bit (9.7 MB)
• Reports: ~/PLFM_RADAR_work/vivado_project/reports_build25/ (21 report files)
• Build log: ~/PLFM_RADAR_work/build25.log
• TCL script: ~/PLFM_RADAR_work/vivado_project/build25_mti.tcl

Note: TCL crashed at step 13/15 (extract_files missing parameter) after all reports were generated. Same non-critical scripting bug as Build 24.

Build 24 — 15-Point Engineering Report

Status: PASS — Production-safe bitstream generated

Date: 2026-03-20  |  Commit: 0745cc4  |  Device: XC7A200T-2FBG484I  |  Vivado 2025.2

1. Timing Summary

TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints.

2. Utilization (Post-Route)

CFAR added +1 BRAM18 (magnitude buffer, 2048×17), +3 DSP48E1 (alpha multiply + cross-multiply for GO/SO), +2,366 LUTs (sliding window logic, state machine, mode mux), +1,320 FFs (pipeline registers, counters, window sums).

3. DSP48E1 Breakdown by Module

4. BRAM Breakdown by Module

5. Power Estimate

+22 mW (+3%) from CFAR logic. Well within thermal budget.

6. Critical Path Analysis

The tightest path (WNS = +0.179 ns) is in the clk_mmcm_out0 (400 MHz) domain: NCO sine LUT index register → LUT6 → sin_abs_reg. This is the same path that was critical in Build 21 and is unrelated to CFAR.

The clk_100m domain (where CFAR operates) has +0.287 ns slack. The Build 23 critical path (cfar_inst/leading_sum → cross-multiply → alpha*noise DSP, WNS = -0.309 ns) has been completely eliminated by the pipeline fix.

7. Post-Synthesis vs Post-Route Comparison

Post-route phys_opt resolved all 29 hold violations and improved setup slack by 56 ps. LUT/FF count reduced slightly by optimization passes.

8. DRC (Design Rule Checks)

184 checks performed. 0 errors, 0 critical warnings. Advisory/warning breakdown:

• DPIP-1 (input pipelining advisory): 68 — DSP input pipeline suggestions, acceptable for our architecture
• DPOP-1/2 (output pipelining): 18 + 19 — DSP PREG/MREG advisory, non-critical
• REQP-1839/1840 (BRAM async control): 20 + 20 — expected with async-reset BRAMs
• RPBF-3 (IO buffering): 8 — intentional for differential pairs
• CHECK-3 (report rule limit): 2 — tool display limit, not design issue
• IOSR-1 (IOB set/reset sharing): 1 — non-critical

9. Methodology Report

• DPIR-1 (async driver): 91 — known from async-reset architecture, mitigated by CDC modules
• HPDR-1 (port direction inconsistency): 8 — bidir USB data bus, expected
• LUTAR-1 (LUT drives async reset): 1 — watchdog reset path, intentional
• PDRC-190 (suboptimal sync register placement): 3 — minor, does not affect timing
• SYNTH-6 (RAM timing sub-optimal): 18 — inferred RAMs, all meeting timing
• TIMING-9 (unknown CDC logic): 1 — covered by explicit CDC synchronizers
• TIMING-28 (auto-derived clock in constraint): 8 — expected with MMCM-derived clocks
• TIMING-47 (false path between sync clocks): 4 — intentional XDC false_path constraints

10. Congestion

No congestion windows found above level 5. The design is well-placed with no routing pressure. XC7A200T provides ample routing resources at 6.36% LUT utilization.

11. Route Status

• Total logical nets: 31,136
• Routable nets: 22,026 — 22,026 fully routed (100%)
• Nets with routing errors: 0

12. Logic Level Distribution (Top 1000 Worst Paths)

The clk_100m domain has only level-0 paths in the top-1000 worst — CFAR pipeline fix reduced logic depth to register-to-register transfers. The 400 MHz DDC domain remains the most timing-critical area.

13. Build-Over-Build Comparison

14. CFAR Integration Resource Cost

Total CFAR cost: 2.82% of device LUTs, 0.48% of FFs, 0.27% of BRAM, 0.41% of DSPs. Minimal impact on headroom.

15. Verification Summary

5,281 individual data checks across all RTL test suites. Zero failures. Real-data co-simulation confirms bit-exact match with Python golden reference across the entire signal processing chain.

Build 24 Artifacts

• Bitstream: ~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build24.bit (9.7 MB)
• Reports: ~/PLFM_RADAR_work/vivado_project/reports_build24/ (21 report files)
• Build log: ~/PLFM_RADAR_work/build24.log
• TCL script: ~/PLFM_RADAR_work/vivado_project/build24_cfar.tcl

Note: TCL crashed at step 13/15 (extract_files missing parameter) after all reports were generated. Non-critical scripting bug; all implementation, optimization, and bitstream generation completed successfully.

Board-day artifact inventory

FPGA implementation analysis

Status: Current engineering baseline — Build 25 (MTI + DC notch)

Build 25 is the current production baseline. Includes MTI canceller (2-pulse clutter cancellation) and DC notch filter on top of CA-CFAR detector. Full 15-point report above. WNS +0.132 ns, WHS +0.058 ns. DSP count 142 (unchanged). BRAM 17 (unchanged). LUTs 9,252 (+694 from Build 24). FFs 12,488 (+2,104). Power 0.753 W (unchanged).

Build 24 (v0.1.5-cfar) integrated CA-CFAR with pipelined noise computation. Build 23 failed timing (WNS -0.309 ns) due to combinational critical path — fixed by pipelining.

Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.

Latest Simulation Report (Recommended)

Status: Current baseline (v2)

File: AERIS_Simulation_Report_v2.pdf

Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.

Open PDF Download

Report Currency Notice

• The current routed production-target baseline is Build 25 with all timing constraints met. WNS +0.132 ns, WHS +0.058 ns, 142 DSP48E1, 17 BRAM, 0.753 W.
• All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes (Build 24). MTI canceller + DC notch filter added in Build 25. Gaps 2–7 were closed prior to Build 21.
• FPGA regression: 23/23 pass (includes CFAR + MTI + E2E tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).
• MTI integration cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSPs. Backward-compatible: host_mti_enable and host_dc_notch_width default to disabled/off.
• Detailed Build 25 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build25/.
• The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.

Antenna concept snapshot