AERIS-10 Docs

Traceability

Release Notes by Key Commit

Milestone notes keyed to major bring-up, debug, and documentation commits.

Commit timeline

Commit Title Impact
TBD v0.1.8-te0713-ft601-dev TE0713/TE0701 + UMFT601X-B FT601 integration dev bitstream First timing-clean FT601 USB integration build for the Trenz + UMFT601X-B FMC LPC stack. Wrapper module (radar_system_top_te0713_umft601x_dev) instantiates the full usb_data_interface with synthetic test data (range/Doppler/CFAR packets). Timing closure achieved after fixing source-synchronous clock skew: replaced set_output_delay with set_max_delay -datapath_only for outputs, removed erroneous set_input_delay on output-only ft601_be[*]. WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors. Strategy: Performance_ExplorePostRoutePhysOpt. Vivado 2025.2. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit.
TBD v0.1.7-te0713-heartbeat TE0713/TE0701 minimal heartbeat bring-up bitstream Created a low-risk bring-up artifact for the Trenz TE0713 + TE0701 stack using radar_system_top_te0713_dev and te0713_te0701_minimal.xdc. Remote Vivado 2025.2 build completed with DRC 0 errors, WNS +17.863 ns, WHS +0.265 ns. Intended as the first board-day image before FT601 arrival and before any radar-path integration.
ed629e7 v0.1.6-mti Build 25: MTI canceller + DC notch filter integration New production baseline. WNS +0.132 ns, WHS +0.058 ns. 9,252 LUTs (6.87%), 12,488 FFs (4.64%), 17 BRAM (4.66%), 142 DSP48E1 (19.19%), 0.753 W. New modules: mti_canceller.v (2-pulse canceller, H(z)=1-z^-1), DC notch filter (inline in system_top). Two new host registers: host_mti_enable (0x26), host_dc_notch_width (0x27). 23/23 FPGA, 20/20 MCU, 3/3 real-data co-sim exact match.
075ae1e v0.1.5-cfar Build 24: CA-CFAR detector integration with pipelined noise computation Prior production baseline. WNS +0.179 ns, WHS +0.056 ns. 8,558 LUTs, 10,384 FFs, 17 BRAM, 142 DSP48E1, 0.754 W. CA/GO/SO CFAR modes with BRAM magnitude buffer, sliding-window algorithm. Host-configurable guard/train/alpha/mode registers (0x21-0x25). Build 23 timing failure fixed by pipelining noise computation. 22/22 FPGA, 20/20 MCU.
e93bc33 v0.1.4-prod-fixes 7 production-quality fixes: detection bugs, digital gain, watchdog, dead code removal Detection sticky flag + magnitude lag fix, rename cfar→threshold_detect, host-configurable digital gain control (power-of-2 shift), Doppler/chirps mismatch protection (clamp + error flag), decimator watchdog timeout, bypass_mode dead code removal, range-mode register (0x20). Real-data co-sim framework added. 22/22 FPGA.
2efab23 v0.1.4-build21 Build 21: FFT opts + E2E RTL fixes + Vivado DRC fix + MMCM LOCKED false_path fix New production baseline. WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns. 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W. Includes 4-cycle FFT butterfly (20% throughput), barrel-shift twiddle (-1 DSP), Vivado DRC multiple-driver fix for data_pending flags, MMCM LOCKED XDC false_path fix (-from → -through). 19/19 FPGA, 20/20 MCU.
0773001 E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring New 46-check E2E testbench (tb_system_e2e.v) across 12 groups. RTL fixes: TX/RX mixer enables mutually exclusive by FSM state, USB write FSM data_pending sticky flags with stream-control reset default 3'b001, STM32 toggle signal wiring for mode-00, dynamic frame detection. USB tests 21/22/56 and regression script PASS/FAIL parsing fixed. 19/19 FPGA, 20/20 MCU.
a3e1996 FFT engine: merge SHIFT into WRITE (4-cycle butterfly) + barrel-shift twiddle index SHIFT state merged into WRITE for 5→4 cycle butterfly (20% throughput gain). Multiplier-based twiddle index replaced with barrel-shift (frees 1 DSP48). Verified via FFT testbench; no timing regression expected.
7cdfa48 Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback Runtime-configurable chirp timing (6 new opcodes 0x10-0x15), stream control gating (opcode 0x04 now gates USB write FSM), CFAR threshold wiring (opcode 0x03 replaces hardcoded value), status readback (opcode 0xFF returns 7-word packet). 4 new TB test groups. 18/18 FPGA, 20/20 MCU regression.
e5d1b3c Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC Wired FT601 read FSM cmd_* outputs through toggle CDC to clk_100m command decode registers. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming. 3 new TB test groups (55 checks). 18/18 FPGA regression.
c6103b3 v0.1.3-build20 Gap 7 MMCM jitter cleaner + CIC CREG pipeline + XDC clock-name fix Added 400 MHz MMCM for ADC clock jitter cleaning, CIC comb DSP48E1 CREG pipeline, and fixed XDC conflicting generated clock. Build 20: WNS +0.426 ns (7x improvement over Build 18). All timing met.
f3bbf77 Gap 3 Safety Architecture IWDG watchdog, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, emergency state ordering. 5 new MCU tests, 20/20 pass.
c87dce0 Gap 5 BRAM async reset fix Fixed chirp memory loader BRAM async reset to use synchronous reset pattern per Xilinx UG901 guidelines.
3b7afba v0.1.2-build18 Build 18 production build Production baseline: WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W.
ed6f79c v0.1.1-build17 FIR DSP48 pipelining + matched filter BRAM migration Build 17 production build with DSP48 pipelining improvements.
c466021 Firmware bug sweep closure (B12-B17) Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage.
49c9aa2 SPI platform fix plus FPGA B2/B3 timing work Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work.
3b32f67 ADF4382A SPI and chip-select correctness Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly.
3979693 Initial 8-firmware-bug closure with tests Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage.

Tagged releases

Architectural gap status

#GapStatus
3Safety ArchitectureDone (f3bbf77)
5BRAM Async ResetDone (c87dce0)
7400 MHz MMCMDone (c6103b3, Build 20)
4USB Read PathDone (e5d1b3c)
2GUI SettingsDone (7cdfa48)
6CDC-15 USB BusesPost-bring-up
1CFAR Real ImplementationDone (075ae1e, Build 24 + MTI in ed629e7)

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